6502 GOES FPGA (AGAIN)

While there has been no shortage of FPGA-based recreations of traditional processors, we always enjoy seeing a new approach. Last month [Some Assembly Required] took on the difficulty to recreate a traditional computer from the ground up as well as started with a 6502 implementation in Verilog. You can see in the second video below that he’s made great development as well as there are obviously more videos to come.

The ROL direction is the subject of the second video. We liked the approach of looking at what the direction does as well as exactly how many cycles it takes on different variants It is always great to make sure you understand precisely what you are trying to achieve before you get started.

We likewise like that the tutorial utilized a few of the more fascinating features of Vivado like automatic verification. even if you are experienced with Verilog, there are some great tips here.

In the end, he’s still a great method from his final goal, however it appears like he’ll get there as well as we’ll be thinking about seeing the rest of the video series as it completes.

The 6502 is a prominent retrocomputing target. one of the tools this job utilizes is the visual 6502 which we’ve covered before. That exact same simulation has ARM1 as well as 6800 targets, too.